On-chip Interconnects
نویسندگان
چکیده
The delay per unit length of on-chip wires, as determined by a diffusive RC-limited response and as measured relative to gate delays, approximately doubles every technology generation as wire resistances per unit length increase and gate delays decrease with scaling. Furthermore, these wire delays (D) grow quadratically with wire length, D ° RwireCwireL. Wire bandwidths, which are inversely proportional to D, degrade.
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